1. Field
The present invention relates to an input buffer of a receiver and, more particularly to an input buffer capable of calibrating an output characteristic in reference voltage variations and an associated method.
2. Related Art
In data transmission, a predetermined reference voltage is used to determine whether a received digital data signal has a logic high state or logic low state. A voltage level of the data signal is compared with a reference voltage externally or internally provided by a receiver's input buffer. The comparison result is transmitted to internal logic of the receiver. The input buffer may have various types. The input buffer for use in a synchronous semiconductor memory device may include a differential amplifier having a current mirror.
FIG. 1 is a circuit diagram of an input buffer 100. Referring to FIG. 1, when an enable signal EN disables the input buffer 100 with a high logic high level (i.e., an inactive state), a transistor MP13 is turned off so that an output signal Vout has a logic low level regardless of a voltage level of an input signal Vin. Conversely, when the enable signal EN enables the input buffer 100 with a logic low level (i.e., an active state), the transistor MP13 is turned on so that current flows through current paths 101 and 102 of the differential amplifier.
When the input signal Vin has a voltage level higher than the reference voltage Vref, an impedance of an NMOS transistor MN12 receiving the input signal Vin is lower than an impedance of an NMOS transistor MN11 receiving the reference voltage Vref so that the output signal Vout has a logic low level. Conversely, when the input signal Vin has a voltage level lower than the reference voltage Vref, the impedance of the NMOS transistor MN12 is higher than the impedance of the NMOS transistor MN11 so that the output signal Vout has a logic high level.
An inverter (not shown) may be disposed at an output terminal so that the output signal Vout may be inverted and transmitted to the internal logic as a final output signal. Therefore, the final output signal may have a logic high level when the input signal Vin has a voltage level higher than the reference voltage Vref and the output signal may have a logic low level when the input signal Vin has a voltage level lower than the reference voltage Vref.
The stability of the reference voltage Vref greatly affects data transmission accuracy. Because a setup time (tDS) and a hold time (tDH) of the input signal Vin may become shorter as the data rate increases, comparison of input signal Vin with the reference voltage Vref may occur at a time different than calculated in the chip's design process, particularly when the reference voltage Vref changes.
Thus, the reference voltage Vref, which needs to be kept stable to verify the reliability of the data transmission, may fluctuate for various reasons. First, signal interference may be caused by parasitic capacitance of a MOS transistor of input buffer that receives the reference voltage Vref, affecting its voltage level. And the reference voltage Vref may be affected by noise on the power supply voltage, manufacturing process, temperature variations, and the like.
When the reference voltage Vref becomes unstable, an operating point of the input buffer becomes unstable affecting a duty of the output signal. More particularly, as a data rate of the semiconductor device increases up to about several gigabits per second (Gbps), capacitance in each transistor increasingly influences the output characteristics of the input buffer. This may cause a problem. The input buffer may not provide an accurate signal to the internal logic, causing errors.
A calibration operation may reduce variations between input and output terminals (DQ) of the semiconductor device and the input buffer to meet the setup time (tDS) and the hold time (tDH) of an AC timing for high-speed data transmission.
FIG. 2 is a circuit diagram of a reference voltage calibrating circuit 200. Referring to FIG. 2, the reference voltage calibrating circuit 200 includes an operational amplifier 211 and capacitors 221, 222, 223, and 224 that are serially coupled to the operational amplifier 211.
The operational amplifier 211 may be configured as a buffer 210 to buffer the reference voltage Vref. The reference voltage Vref may be externally provided or alternatively, generated using an internal reference voltage generating source. Using the serially coupled capacitors 221, 222, 223 and 224, the buffered reference voltage Vref is divided to generate a plurality of reference voltages Vref1, Vref2 and Vref3. The capacitors 221, 222, 223 and 224 may be replaced with resistors or other known circuit components. An advantage of using capacitors 221, 222, 223 and 224 is reduced chip area relative to other circuit components.
The reference voltages Vref1, Vref2 and Vref3 may be selected according to a control signal and provided to the input buffer.
Although the reference voltage calibrating circuit may be implemented in a variety of configurations according to design constraints, one or two reference voltage calibrating circuits may be allotted to eight input and output terminals (DQ) to provide the reference voltage to each input and output terminal (DQ).
The reference voltage calibrating circuit requires as many capacitors as the required number of selectable reference voltage levels. The chip's layout area, therefore, increases accordingly. And noise generated in the operational amplifier 211 may adversely influence the input buffer.
The voltage calibrating circuit increases power consumption due to the use of the operational amplifier 211 and the capacitors 221, 222, 223 and 224.